Two solutions for implementing interconnection between CPUs are as follows.
One implementation solution is interconnection between CPUs that is implemented by the IBM Corporation in a PCB (Printed Circuit Board, printed circuit board) full direct connection manner. Each Power CPU of IBM has 7 high-speed interconnection interfaces, which may be interconnected with 7 Power CPUs at the same time. The 8 Power CPUs may form an 8P system through the full direct connection manner. However, as the Power CPU integrates a function of a NC (node controller), the cost is high. Limited by the number of the interconnection interfaces of the Power CPU, the expansibility of a CPU system that is formed by the Power CPUs is poor, and the flexibility is low.
Another implementation solution is interconnection between CPUs that is implemented by the HP Company by employing a NC node controller and a switch module, and a system of the whole interconnection architecture is complex. In this solution, 2 chips are added in the whole system, which respectively implement NC node control and a switch module function. In this the solution, the switch module is employed to perform an exchange of data between NCs, and each switch module needs to perform jump point judgment, so a delay in data transmission is increased, the system performance is relatively low, and the cost is relatively high.
Therefore, for a current CPU interconnection solution, the expansibility is poor, the delay in data transmission is relatively long, and the system performance is low; in addition, in each link for implementing CPU interconnection, if any link is erroneous, abnormity of the interconnection between the involved CPUs may be caused, and a related solution for interconnection fault tolerance between the CPUs does not exist.